91 p4c164/164l features full cmos, 6t cell high speed (equal access and cycle times) C 8/10/12/15/20/25 ns (commercial) C 10/12/15/20/25/35 (industrial) C 12/15/20/25/35/45 ns (military) low power operation C 770mw active C15 C 660/743 mw active C 20 C 495/575 mw active C 25, 35, 45 C 193/220 mw standby (ttl input) C 5.5mw standby (cmos input) p4c164l (military) output enable and dual chip enable control functions single 5v 10% power supply data retention with 2.0v supply, 10 m a typical current (p4c164l military) common data i/o fully ttl compatible inputs and outputs standard pinout (jedec approved) C 28-pin 300 mil dip, soj C 28-pin 600 mil ceramic dip C 28-pin 350 x 550 mil lcc C 28-pin cerpack p4c164/p4c164l ultra high speed 8k x 8 static cmos rams description the p4c164 and p4c164l are 65,536-bit ultra high-speed static rams organized as 8k x 8. the cmos memories require no clocks or refreshing and have equal access and cycle times. inputs are fully ttl-compatible. the rams operate from a single 5v 10% tolerance power supply. with battery backup, data integrity is maintained with supply voltages down to 2.0v. current drain is typically 10 m a from a 2.0v supply. access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. in full standby mode with cmos inputs, power consumption is only 5.5 mw for the p4c164l. the p4c164 and p4c164l are available in 28-pin 300 mil dip and soj, 28-pin 600 mil ceramic dip, and 28-pin 350 x 550 mil lcc packages providing excellent board level densities. functional block diagram pin configurations 1519b a 0 nc a 2 a 3 a 4 a 5 a 6 a 7 a 8 ce 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a 11 a 9 ce 2 i/o i/o i/o 1519b gnd we 10 a a 12 oe v cc 1 2 3 1 i/o 8 i/o 7 i/o i/o 5 i/o 4 6 a 1 a 2 nc a 4 a 5 a 6 a 7 a 8 i/o 1 ce ce 2 a 12 a 11 a 10 gnd a 0 a 1 v cc 26 25 24 23 22 21 20 4 5 6 7 8 9 10 11 12 19 18 13 17 327 1 15 2 14 28 16 i/o 2 a 9 oe i/o 8 i/o 7 we i/o 3 i/o 4 i/o 5 i/o 6 a 3 1 1519c 1519a input data control row select 65,536-bit memory array column i/o i/o 1 i/o 8 column select we oe a 0 a 7 a 8 a 12 ce 1 ce 2 ????? ??? ??? ??? ?????
92 p4c164/164l
93 p4c164/164l data retention characteristics (p4c164l, military temperature only) typ.* max symbol parameter test condition min v cc =v cc = unit 2.0v 3.0v 2.0v 3.0v v dr v cc for data retention 2.0 v i ccdr data retention current 10 15 200 300 m a t cdr chip deselect to 0 ns data retention time t r ? operation recovery time t rc ns * t a = +25 c t rc = read cycle time ? this parameter is guaranteed but not tested. i cc symbol parameter temperature range dynamic operating current* commercial industrial military n/a n/a C10 n/a C8 C12 C15 C20 C25 C35 C45 unit n/a ma ma ma *v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce 1 = v il , ce 2 = v ih , oe = v ih power dissipation characteristics vs. speed v cc t cdr 4.5v v dr 3 2v 4.5v t r data retention mode v hc v dr ce ce 1 2 v lc v hc v lc data retention waveform ce 1 3 v cc C 0.2v or ce 2 0.2v, v in 3 v cc C 0.2v or v in 0.2v 190 150 155 160 170 180 180 170 160 155 150 145 200 180 170 160 155 150 n/a n/a
94 p4c164/164l
95 p4c164/164l t address data out aa t t oh data valid previous data valid (9) rc read cycle no. 2 (address controlled) (5,6) read cycle no. 3 ( ce ce ce ce ce 1 , ce 2 controlled) (5,7,10) notes: 9. read cycle time is measured from the last valid address to the first transitioning address. t ce data out ac t rc t lz data valid i cc i sb t pu high impedance t pd (8,10) (8,10) t hz supply cc current v ce (10) (10) (10) 2 1 10. transitions caused by a chip enable control have similar delays irrespective of whether ce 1 or ce 2 causes them.
96 p4c164/164l
97 p4c164/164l t t we address ce data out data in t wc data valid high impedance (14) t as t cw t aw t wp dw ah wr t dh t 1 ce 2 (11) timing waveform of write cycle no. 2 ( ce ce ce ce ce controlled) (11) mode ce ce ce ce ce 1 ce 2 oe oe oe oe oe we we we we we i/o power standby h x x x high z standby standby x l x x high z standby d out disabled l h h h high z active read l h l h d out active write l h x l high z active ac test conditions input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 truth table figure 1. output load figure 2. thevenin equivalent (12) * including scope and test fixture. note: because of the ultra-high speed of the p4c164/l, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 m f high frequency capacitor is also required between v cc and ground. to avoid signal olz d out 255 w 480 w +5v 30pf* (5pf* for t hz , t lz t wz ow and t , ) t ohz t , , 30pf* (5pf* for t hz , t lz t wz ow and t , ) d out 166.5 w v th = 1.73 v = r th , t ohz , t olz , reflections, proper termination must be used; for example, a 50 w test environment should be terminated into a 50 w load with 1.73v (thevenin voltage) at the comparator input, and a 116 w resistor must be used in series with d out to match 166 w (thevenin resistance).
98 p4c164/164l
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